Itanium
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[edit] Description
HP and Intel first collaborated on chip for servers and workstations in 1989. HP needed a next generation replacement for its successful PA-RISC line of servers and workstations, and wanted to tap Intel's volume and expertise in chip design and manufacturing.
It would use Explicitly Parallel Instruction Computing where the compiler would line up instructions for parallel execution. Features were added to ensure compatibility with both Intel x86 and HP applications.
However, performance was disappointing. In IA-64 mode, it performed only slightly better than an equivalently clocked x86 design, and when running legacy x86 code, performance was extremely poor, about 1/8th that of a similarly clocked x86 processor. Software emulation would have been faster.
The main (though by no means only) structural design flaw with the Itanium was the high latency of its level three cache. Intel's engineers had evidently been hoping that the amount of bandwidth available would offset this, but the latency was so high that it actually slowed the cache, to the point where it was not significantly faster than the main memory interface.
It was succeeded by the Itanium 2
[edit] Table of parameters
| Vendor | Intel |
|---|---|
| Designer | Intel / HP |
| Architecture/Family | Scalar / Intel IA-64 |
| Processor Generation | Itanium |
| Core name | Merced |
|---|---|
| Model name(s) | Itanium |
| Time of manufacture | 2001.06 |
| Theoretical perfomance | up to 3.2 GFLOPS |
| Multiple Cores | no |
| Core frequency | 733-800 MHz |
| Manufacture Technology | 180nm |
|
Cache: L1 (Data + Instructions) / L2 / L3 | L1 32KB / L2 96KB / L3 2Mb or 4MB on-cartridge |
| Front Side Bus | 2x133 MHz / 4.2 GB/s |
| Socket/Package | PAC418 / FCPGA, 418 pins |
| SMP Capabilities | 4-way glueless |
| Power consumption | 116,0W-130,0W / 71,4A |
| Voltage | 1.8 V |
| Quantity of transistors | 25M |
| Area of chip | 300mm² |
| Instruction sets | CISC, IA64, MMX, SSE |
| Affiliated technologies | EPIC |
| FPU / ALU / load-store units | 2x / 4x / 1x-1x |
| Instruction pipeline | 10 |
|
Address space physical / virtual | 44-bit / 54-bit |
| Floating-Point formats | 32, 64, 80, 128-bit under HP-UX |
| Chipsets | 460GX Chipset |
