Paragon XP/S
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[edit] Description
Paragon XP/S was a productized version of the experimental Touchstone Delta system built at CalTech, launched in 1992. The Paragon superseded Intel's earlier iPSC/860 system, to which it was closely related.
The Paragon series was based around the i860 RISC microprocessor. Up to 2048 (later, up to 4000) i860s were connected in a 2D grid. In 1993, an entry-level Paragon XP/E variant was announced with up to 32 processors.
Intel intended the Paragon to run the OSF/1 AD distributed operating system on all processors. However, this was found to be inefficient in practice, and a light-weight kernel called SUNMOS was developed at Sandia National Laboratories to replace OSF/1 AD on the Paragon's compute processors.
In 1993 the Paragon XP/S 140 installed at the Sandia National Laboratories was ranked #1 in the TOP500 list with 140 GFlops and 3680 CPU.
In 1995 the MP (Multi Processor) node was introduced. In such an MP node 3 i860/XP processors reside on one board and the processors share one address space. Fortran and C compilers take care of the automatic parallelisation within a MP node.
[edit] Information Tables
| Vendor | Intel |
|---|---|
| System designer | Intel |
| Model name(s) | Paragon XP/S |
| Time of manufacture | 1992 |
| Number of systems sold | ~30 by 1993.09 |
| Resellers | - |
| GENERAL INFORMATION | |
|---|---|
| Class | MPP |
| Type | RISC-based distributed-memory multi-processor |
| Operating system | OSF/1, SUNMOS |
| Compilers | Fortran 77, High Performance Fortran preprocessor, C, C++, ADA |
| Other specific software | Virtual File System, Distributed File System, Parallel File System, FORGE 90, XIPD (Interact. Parallel Debugger), Xgprof (profiling), ParaGraph, SPV (System Performance Visualization Tool), PVM, EXPRESS, PARMACS, TCGMSG (portable message passing libraries), ProSolver (parallel mathematical library) |
| Affiliated technologies | - |
| CPU generation used | Intel i860 |
| CPU model | 50MHz/75MFLOPS i860XP |
| DRAM type | 4-Mbit, 60ns DRAM chips, SECDED error handling (400 MB/s bandwidth to cache) |
| FPGA | n/a |
| System cooling | Air |
| Floor space | 56x107 cm per cabinet |
| NETWORK | |
| Node Interconnect | NIC with 4 external links (175 MB/s in each direction, 30µs latency) |
|
Network switch / Size / Quantity | n/a |
| Network topology | 2-D mesh (torus) |
| Management network | Ethernet, HiPPI, FDDI |
| BUILDING BLOCKS | ||||
|---|---|---|---|---|
| Block name --> | GP Node | MP Node | Cabinet | System |
| Structure | basic block | basic block | 64 nodes | - |
| Number of CPU | 2 | 3 | GP: 64, MP: 192 | up to 4000 |
| Memory size (max) | 16MB or 32MB | - | - | up to 128GB |
| Other equipment | Message Processor: second i860 XP | - | MIO node with RAID levels 3, 5 (5xHDD) | QIC-150 streamer |
| Power consumption | - | - | ~ 5 kW | - |
| Theor.performance | 75 Mflops | 225 Mflops | - | up to 300 Gflops |
| BENCHMARKS | ||||
|
HPL Benchmark: CPUs / Rmax / efficiency / Date | - | - | - | 3680 CPU (XP/S140) / 143.4 GF / 52% / 1993 |
| Application performance | - | - | - | - |
