CM-5
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[edit] Description
The Connection Machine 5 (CM-5) was developed by the Thinking Machine Corporation located in Cambridge Massachusetts.
The basic computational node of the CM-5 consists of a SPARC processor of which in turn the performance can be enhanced by adding up to 4 vector units manufactured by Texas Instruments. Such a maximal node should deliver 128 Mflop/s in 64-bit precision.
Apart from the computational processors, so-called Control Processors (CPs) can be configured (the amount depending on the size of the configuration). CPs handle system tasks, I/O requests, etc. For I/O processors there is an analog possibility.
The CM-5 has several networks. There are a control- and a data network. As the name suggests, the first is used for synchronisation and control, while the second one is used for massive data movement. A "fattened tree" topology is employed, i.e., a tree structure that scales the bandwidth with the distance to the root in three levels, each nearer level being having a bandwidth which is twice that of the more distant level. This overcomes to some extent the bandwidth problems as found in normal trees. At the first level the communication speed is 20 MB/s (10 MB/s/wire; 2 wires/node), at the second level this speed is halved to 10 MB/s, while for all higher levels the speed is again halved to 5 MB/s.
[edit] Information Tables
| Vendor | TMC |
|---|---|
| System designer | TMC |
| Model name(s) | CM-5 |
| Time of manufacture | 1992-1996 |
| Number of systems sold | - |
| Resellers | - |
| GENERAL INFORMATION | |
|---|---|
| Class | MPP |
| Type | Distributed-memory multi-vector processor |
| Operating system | CMost (TMCs Unix variant) |
| Compilers | CM Fortran (Fortran 90 like), C* and *Lisp with parallel extensions |
| Other specific software | - |
| Affiliated technologies | - |
| CPU generation used | SPARC |
| CPU model | 32MHz / 128Mflops CM-5 CPU with 4 vector units |
| DRAM type | - |
| FPGA | n/a |
| System cooling | - |
| Floor space | - |
| NETWORK | |
| Node Interconnect | two 10MB/s wires per node |
|
Network switch / Size / Quantity | - |
| Network topology | Hypercube, fat tree |
| Management network | yes |
| BUILDING BLOCKS | |||
|---|---|---|---|
| Block name --> | Node | Cabinet | System |
| Structure | basic block | - | 16 - 1024 nodes (up to 16384 nodes theoretically) |
| Number of CPU | 1 | - | up 16 - 1024 (up to 16384 CPU theoretically) |
| Memory size (max) | 32 MB | - | up to 524GB |
| Other equipment | 1 NIC | - | - |
| Power consumption | - | - | 5 kW for 1024 nodes |
| Theor.performance | 128 Mflops | - | - |
| BENCHMARKS | |||
|
HPL Benchmark: CPUs / Rmax / efficiency / Date | - | - | 1024 CPU / 59.7GF / 45.6% / 1995 |
| Application performance | - | - | - |
