Blue Gene
From TOP500 Supercomputing Sites - Wiki
[edit] Description
Blue Gene/L is a computer architecture project designed to produce several next-generation supercomputers, designed to reach operating speeds in the petaflops range, and currently reaching speeds over 280 teraflops (sustained). It is a cooperative project between the United States Department of Energy (which is partially funding the project), industry (IBM in particular), and academia.
Each Compute or IO node is a single ASIC with associated DRAM memory chips. The ASIC integrates two 700 Mhz PowerPC 440 embedded processors, each with a double-pipeline-double-precision Floating Point Unit (FPU), a cache sub-system with built-in DRAM controller and the logic to support multiple communication sub-systems. The dual FPUs give each Blue Gene/L node a theoretical peak performance of 5.6 GFLOPS. It is possible to use only one of the CPUs on a chip for computation and reserve the other one for communication tasks.
Blue Gene/L compute nodes use a minimal operating system supporting a single user program. To allow multiple programs to run concurrently, a Blue Gene/L system can be partitioned into electronically isolated sets of nodes. The number of nodes in a partition must be a positive integer power of 2, and must contain at least 32 nodes.
MTBF time of the largest system installation is about 6.16 days (dominated by memory failure).
[edit] Information Tables
| Vendor | IBM |
|---|---|
| System designer | IBM |
| Model name(s) | Blue Gene |
| Time of manufacture | 2004 |
| Number of systems sold | 158 racks (34 customer sites) as of 2007.08 |
| GENERAL INFORMATION | |
|---|---|
| Class | Cluster |
| Type | RISC-based distributed-memory multi-processor |
| Operating system | Linux |
| Compilers | XL Fortran (Fortran 90), XL C, C++ |
| Other specific software | ESSL, MASS, MASSV, MPICH2 |
| Affiliated technologies | system-on-a-chip |
| CPU generation used | PowerPC 440 |
| CPU model | 700MHz CPU (system-on-a-chip) |
| DRAM type | DDR SDRAM 350MHz |
| FPGA | n/a |
| System cooling | Air |
| Floor space | 2500 ft? / ~300tons in full configuration |
| NETWORK | |
| Node Interconnect | Proprietary / 6x175MB/s 3D Torus , 350MB/s Tree |
|
Network switch / Size / Quantity | - |
| Network topology | 3D torus and tree network |
| Management network | - |
| BUILDING BLOCKS | |||||
|---|---|---|---|---|---|
| Block name --> | Node | Compute Card | Node Board | Cabinet | System |
| Structure | basic block | 2 Nodes | 16 Compute Cards | 32 Node Boards | up to 64 Cabinets |
| Number of CPU | 2 (in single chip) | 4 | 64 | 2048 | 131072 |
| Memory size (max) | cache | 1GB | 16GB | 512GB | 32TB |
| Other equipment | - | - | 0-2 I/O cards | - | - |
| Power consumption | 10-15W | - | - | 15-20KW | 1.2-1.5MW |
| Theor.performance | 2.8/5.6GF | 5.6/11.2GF | 89.6/179.2GF | 2.9/5.7TF | 180/367TF |
| BENCHMARKS | |||||
|
HPL Benchmark: CPUs / Rmax / efficiency / Date | - | - | - | - | 131072xCPU /280.6TF / 76.45% / 2005 8192xCPU / 18.2TF / 79.4% / 2005 |
| Application performance | - | - | - | - | - |
